module tb_ula;

reg [8:0] a;
reg [8:0] b;
reg [0:0] sel;
wire [8:0] result;

initial begin
    $from_myhdl(
        a,
        b,
        sel
    );
    $to_myhdl(
        result
    );
end

ula dut(
    a,
    b,
    sel,
    result
);

endmodule
